Secure scan entry

An integrated circuit, comprising:

• a secure domain, comprising flip-flops that contain confidential or proprietary information,
• a first signal that denotes that the integrated circuit is in a test mode;
• a second signal;
• and
• a secure domain protection circuit, wherein the secure domain protection circuit issues a reset to the flip-flops in the secure domain during a time interval between an assertion of the first signal and an assertion of the second signal.

A method of performing a secure scan test of an integrated circuit, the integrated circuit comprising a secure domain comprising flip-flops that contain confidential or proprietary information and a scan configuration circuit that selects a desired test mode configuration;

• the method comprising:
• asserting a SCAN_TEST_EN signal to place the integrated circuit in test mode, wherein the assertion of the SCAN_TEST_EN issues a reset to the flip-flops in the secure domain;
• inputting the desired test mode by presenting data to the integrated circuit;
• storing the desired test mode in the scan configuration circuit by asserting a SCAN_TST_UPDATE signal, wherein the assertion of the SCAN_TST_UPDATE signal also terminates the reset to the flip-flops in the secure domain;
• and
• performing the scan test after the desired test mode is stored.