Methods, apparatus and electronic devices for absolute time synchronization

A method of absolute time synchronization, wherein, the method is executed on a timing chip of a terminal in a mobile network, the method comprising:

• performing a first timing signaling processing step, comprising receiving, from a baseband processing chip, a first timing signaling and a first real system frame information used by a base station for transmitting the first timing signaling to the terminal, wherein the first timing signaling comprises a first absolute time corresponding to local time of the base station at time of transmission of the first timing signaling and a first reference system frame information used by the base station for transmitting the first timing signaling;
• calculating an initial time delay adjustment value between the base station and the terminal based on at least the first absolute time, if the first real system frame information is consistent with the first reference system frame information;
• starting a virtual state machine, which enters an initial state of the virtual state machine;
• wherein, in the initial state, a first time delay between the base station and the terminal is determined as the initial time delay adjustment value, a total time delay adjustment value is set to 0, and then the virtual state machine enters a first state.
• performing a subsequent timing signaling processing step, comprising:
• receiving, from the baseband processing chip, a subsequent timing signaling and a second real system frame information used by the base station for transmitting the subsequent timing signaling, wherein the subsequent timing signaling comprises a second absolute time corresponding to the local time of the base station at time of transmission of the subsequent timing signaling, and a second reference system frame information used by the base station for transmitting the subsequent timing signaling;
• determining a time delay adjustment value between the subsequent timing signaling and the first timing signaling based on at least the first time delay and the second absolute time, if the second real system frame information is consistent with the second reference system frame information;
• adding 1 to a number of the received subsequent timing signalings, and enabling the virtual state machine to move from the current state to a second state, the current states comprising the first or the second state;
• wherein:
• in the second state, if the time delay adjustment value of the subsequent timing signaling is greater than or equal to the second jitter threshold, the number of the subsequent timing signalings is decreased by 1 and the current state of the virtual state machine moves from the second state to the first state;
• after moving from the second state to the first state, if the time delay adjustment value of the subsequent timing signaling is greater than or equal to the first jitter threshold, the number of the subsequent timing signalings is reset to 0, the first time delay is reset to 0, and the current state of the virtual state machine moves from the first state to the initial state, first timing signaling processing step is performed;
• on the other hand, after moving from the second state to the first state, if the time delay adjustment value of the subsequent timing signaling is less than the first jitter threshold, the total time delay adjustment value is increased by a weighted value of the time delay adjustment value, which is less than the time delay adjustment value, and if the number of subsequent timing signaling is less than a target number, the subsequent timing signaling processing step is performed, and if the number of the subsequent timing signaling is equal to the target number, an absolute time information outputting step is performed;
• and
• in the second state, if the time delay adjustment value of the subsequent timing signaling is less than the second jitter threshold, the total time delay adjustment value is increased by the time delay adjustment value of the subsequent timing signaling, and the number of the subsequent timing signalings is increased by 1, and if the number of the subsequent timing signalings is less than the target number, the subsequent timing signaling processing step is performed, and if the number of the subsequent timing signalings is equal to the target number, the absolute time information outputting step is performed;
• the absolute time information outputting step comprises:
• determining an absolute time information based on the total time delay adjustment value, the number of the subsequent timing signalings and the first time delay and outputting the absolute time information, which is used to synchronize the time of terminal to time of the base station.