System and method for performing netlist obfuscation for a semiconductor device
AssigneeNXP B.V.
InventorJan-Peter SCHAT
Life of this patent
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Abstract
A tie cell includes a first flip-flop having a physically unclonable function (PUF), a second flip-flop that generates a PUF key value, and logic that logically combines the PUF value and the PUF key value to generate an output signal having a constant logical value. The PUF value is based on a power-up value stored in the first flip-flop, which power-up value is generated based on physical and/or electrical characteristics produced from a manufacturing process. The output value is generated to tie digital logic to the constant logical value.
Claims20
A tie cell, comprising:
- a first flip-flop including a physically unclonable function (PUF);
- a second flip-flop configured to generate a PUF key value;
- and
- logic configured to combine a value of the PUF and the PUF key value to generate an output signal having a constant logical value, wherein the PUF value is based on a power-up value stored in the first flip-flop, the power-up value generated as a result of physical and/or electrical characteristics produced from a manufacturing process, and wherein the output value is generated to tie digital logic to the constant logical value.
An integrated circuit, comprising:
- a first tie cell configured to generate a first signal;
- a second tie cell configured to generate a second signal;
- and
- a controller configured to generate at least one control signal for one or both of the first tie cell and the second tie cell, wherein the first tie cell embodies a first physically unclonable function (PUF) and the second tie cell includes a second PUF different from the first PUF and wherein the first signal has a constant first logical value and the second signal has a constant second logical value different from the first logical value.
A method for controlling an integrated circuit, comprising:
- obtaining a value correspond to a physically unclonable function (PUF);
- generating a PUF key value based on the PUF value;
- and
- logically combining the PUF value and the PUF key value to generate an output signal having a constant logical value, wherein the PUF value is based on a power-up value stored in a first flip-flop in a tie cell, the power-up value generated as a result of physical and/or electrical characteristics produced from a manufacturing process, and wherein the output value is generated to tie digital logic to the constant logical value.
Dependencies are inferred from the claim text.