Electronic device with bit pattern generation, integrated circuit and method for polar coding

An integrated circuit for an electronic device configured to perform polar coding, the integrated circuit comprising:

• a bit pattern generator configured to successively perform a bit pattern generation process over a series of clock cycles;
• wherein the bit pattern generator is configured to:
• provide a successive sub-set of (w) bits from a bit pattern vector (bk,n) in each successive clock cycle;
• where the bit pattern vector comprises n bits, of which ‘k’ bits adopt a first binary value and n−k bits adopt a complementary binary value and wherein the bit pattern generator comprises a bank of (w) comparators, and wherein the successive sub-set of w bits cause each of w bit pattern bits {b0, b1, b2, . . . , bm−1} to be obtained from a corresponding comparator in the bank of ω comparators, and wherein a rank vector, Rn, for a length of the bit pattern, ‘n’, comprises integers in a range of ‘0’ to ‘n−1’, permuted in an order that corresponds to a rank of each bit position, and wherein the bit pattern vector, bk,n, is generated for a respective combination of the number, k, of bits in a bit pattern adopting the first binary value and the length of the bit pattern ‘n’ using the bank of w comparators that compares each element of the rank vector, Rn with ‘k’.

A method of polar coding, wherein the method comprises:

• successively performing a bit pattern generation process over a series of clock cycles by a bit pattern generator;
• and
• providing a successive sub-set of w bits from a bit pattern vector, bk,n, in each successive clock cycle;
• where the bit pattern vector comprises ‘n’ bits, of which ‘k’ bits adopt a first binary value and n−k bits adopt a complementary binary value and wherein the bit pattern generator comprises a bank of w comparators, and wherein the successive sub-set of (w) bits cause each of w bit pattern bits {b0, b1, b2, . . . , bw−1} to be obtained from a corresponding comparator in the bank of w comparators, and wherein a rank vector, Rn, for a length of the bit pattern, ‘n’, comprises integers in a range of ‘0’ to ‘n−1’, permuted in an order that corresponds to a rank of each bit position, and wherein the bit pattern vector, bk,n, is generated for a respective combination of the number, k, of bits in a bit pattern adopting the first binary value and the length of the bit pattern ‘n’ using the bank of w comparators that compares each element of the rank vector, Rn with ‘k’