Bit-flipping decoder architecture for irregular quasi-cyclic low-density parity-check codes

A system for reducing complexity of a decoder, comprising:

• a processor and a memory including instructions stored thereupon, wherein the instructions upon execution by the processor cause the processor to:
• receive a noisy codeword that is based on a transmitted codeword generated from an irregular quasi-cyclic low-density parity-check (QC-LDPC) code, the irregular QC-LDPC code having an associated parity matrix;
• store, based on a weight of a plurality of columns of the parity matrix of the irregular QC-LDPC code, a portion of the noisy codeword corresponding to the plurality of columns in a first buffer of a plurality of buffers;
• and
• access and process the portion of the noisy codeword that includes applying a vertically shuffled scheduling (VSS) scheme that uses a plurality of processing units to determine a candidate version of a portion of the transmitted codeword that corresponds to the portion of the noisy codeword,
• wherein the processing comprises a performing a message passing algorithm between a plurality of variable nodes and a plurality of check nodes that represent the parity matrix of the irregular QC-LDPC code,
• wherein the VSS scheme processes each of the variable nodes one by one in each iteration of the message passing algorithm, and
• wherein a number of the plurality of processing units is based on a distribution of column weights in the parity matrix.

A non-transitory computer-readable storage medium having instructions stored thereupon for reducing complexity of a decoder, comprising:

• instructions for receiving a noisy codeword that is based on a transmitted codeword generated from an irregular quasi-cyclic low-density parity-check (QC-LDPC) code, the irregular QC-LDPC code having an associated parity matrix;
• instructions for storing, based on a weight of a plurality of columns of the parity matrix of the irregular QC-LDPC code, a portion of the noisy codeword corresponding to the plurality of columns in a first buffer of a plurality of buffers;
• and
• instructions for accessing and processing the portion of the noisy codeword that includes applying a vertically shuffled scheduling (VSS) scheme that uses a plurality of processing units to determine a candidate version of a portion of the transmitted codeword that corresponds to the portion of the noisy codeword,
• wherein the processing comprises a performing a message passing algorithm between a plurality of variable nodes and a plurality of check nodes that represent the parity matrix of the irregular QC-LDPC code,
• wherein the VSS scheme processes each of the variable nodes one by one in each iteration of the message passing algorithm, and
• wherein a number of the plurality of processing units is based on a distribution of column weights in the parity matrix.