US 2021/0242844 A1Published application

Operational amplifier input stage with high common mode voltage rejection

AssigneeTexas Instruments Incorporated

InventorsVadim Valerievich Ivanov, Srinivas Kumar Pulijala

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Abstract

An apparatus has four transistors. The first and third transistors each have a gate coupled to a first input terminal and second input terminal respectively, a source coupled to a current source and to a first terminal of a bias voltage source, and a substrate coupled to a second terminal of the bias voltage source. The second and fourth transistors each have a gate coupled to the first input terminal and the second input terminal respectively, a source coupled to the drain of the first and third transistors respectively, a drain coupled to a lower voltage supply and a substrate coupled to its source. The bias voltage source increases the threshold voltages of the first and third transistors above the second and fourth transistors, respectively. This ensures that the first and third transistors turn on after the second and fourth transistors, respectively.

Claims20

Dependent claims

An apparatus comprising:

a first transistor having a first gate, a first source, a first drain, and a first substrate;
in which the first gate is coupled to a first input terminal;
in which the first source is coupled to a current source;
and
in which the first substrate is coupled to a bias voltage terminal;
a second transistor having a second gate, a second source, a second drain, and a second body;
in which the second gate is coupled to the first input terminal;
in which the second source is coupled to the first drain;
in which the second drain is coupled to a first output terminal;
and
in which the second substrate is coupled to the second source;
a third transistor having a third gate, a third source, a third drain, and a third substrate;
in which the third gate is coupled to a second input terminal;
in which the third source is coupled to the current source;
and
in which the third substrate is coupled to the bias voltage terminal;
and
a fourth transistor having a fourth gate, a fourth source, a fourth drain, and a fourth substrate;
in which the fourth gate is coupled to the second input terminal;
in which the fourth source is coupled to the third drain;
in which the fourth drain is coupled to a second output terminal;
and
in which the fourth substrate is coupled to the fourth source.

20 more elements

An apparatus comprising:

a first transistor having a first gate, a first source, a first drain, and a first substrate;
in which the first gate is coupled to a first input terminal;
in which the first source is coupled to a current source and to a first terminal of a bias voltage source;
and
in which the first substrate is coupled to a second terminal of the bias voltage source;
a second transistor having a second gate, a second source, a second drain, and a second substrate;
in which the second gate is coupled to the first input terminal;
in which the second source is coupled to the first drain;
in which the second drain is coupled to a lower voltage supply;
and
in which the second substrate is coupled to the second source;
a third transistor having a third gate, a third source, a third drain, and a third substrate;
in which the third gate is coupled to a second input terminal;
in which the third source is coupled to the current source and to the first terminal of the bias voltage source;
and
in which the third substrate is coupled to the second terminal of the bias voltage source;
a fourth transistor having a fourth gate, a fourth source, a fourth drain, and a fourth substrate;
in which the fourth gate is coupled to the second input terminal;
in which the fourth source is coupled to the third drain;
in which the fourth drain is coupled to the lower voltage supply;
and
in which the fourth substrate is coupled to the fourth source.

19 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/777,521Filed 30 Jan 2020
Published: 5 Aug 2021
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

H03F 3/45076
With semiconductor devices only: characterised by the way of implementation of the active amplifying circuit in the differential amplifier
H03F 3/45183
Using MOSFET transistors as the active amplifying circuit: long tailed pairs
H03F 3/45188
Long tailed pairs: non-folded cascode stages
H03F 3/45632
Characterised by the way of common mode signal rejection: in differential amplifiers with FET transistors as the active amplifying circuit

Family

US 11,251,759 B2Related patent
US 2021/0242844 A1This patent

From the US filing history. Foreign family members aren’t listed.

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