Bias arrangements for improving linearity of amplifiers

A bias arrangement for an amplifier, the bias arrangement comprising:

• a first transistor, configured to provide, at an output of the first transistor, a bias signal for the amplifier;
• a second transistor;
• and
• a third transistor,
• wherein:
• the output of the first transistor is coupled to an input of the second transistor,
• an output of the second transistor is coupled to an input of the first transistor,
• the output of the second transistor is further coupled to an input of the third transistor, and
• the third transistor is configured to provide, at an output of the third transistor, a modified bias signal to be provided to the amplifier, where the modified bias signal is based on the bias signal provided at the output of the first transistor.

A bias arrangement for an amplifier, the bias arrangement comprising:

• a first transistor, configured to provide, at an output of the first transistor, a bias signal for the amplifier;
• a second transistor;
• a third transistor;
• and
• a fourth transistor,
• wherein:
• the output of the first transistor is coupled to an input of the second transistor,
• an output of the second transistor is coupled to an input of the first transistor,
• the output of the second transistor is further coupled to each of an input of the third transistor and an input of the fourth transistor,
• the third transistor is configured to provide, at an output of the third transistor, a first modified bias signal to be provided to a first input of the amplifier, where the first modified bias signal is based on the bias signal provided at the output of the first transistor, and
• the fourth transistor is configured to provide, at an output of the fourth transistor, a second modified bias signal to be provided to a second input of the amplifier, where the second modified bias signal is based on the bias signal provided at the output of the first transistor.