US 2021/0242690 A1Published application

Semiconductor device and operating method of semiconductor device

AssigneeSemiconductor Energy Laboratory Co., Ltd.

InventorsYuki OKAMOTO, Takahiko ISHIZU

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Abstract

To provide a battery control circuit with a novel structure, a battery protection circuit with a novel structure, and a power storage device including the battery circuit. The semiconductor device includes n cell-balance circuits (n is an integer greater than or equal to 1). One secondary battery is electrically connected to one cell-balance circuit. The cell-balance circuit includes a comparison circuit, and a memory element is electrically connected to an inverting input terminal of the comparison circuit. The memory element includes a first transistor and a capacitor. A potential is retained. The retained potential changes in accordance with a change in a potential of a negative electrode of the secondary battery. The comparison circuit has a function of comparing the retained potential with a potential of a positive electrode of the secondary battery. Output from the comparison circuit controls a gate voltage of a second transistor electrically connected to the secondary battery in parallel. The first transistor includes a metal oxide including indium in a channel formation region.

Claims11

Dependent claims

A semiconductor device comprising n cell-balance circuits,

wherein n is an integer greater than or equal to 1,
wherein the n cell-balance circuits are electrically connected to n secondary batteries,
wherein one of the n secondary batteries is electrically connected to one of the n cell-balance circuits,
wherein each of the n cell-balance circuits comprises:
a comparison circuit;
a first terminal electrically connected to a non-inverting input terminal of the comparison circuit;
a first transistor one of a source and a drain of which is electrically connected to an inverting input terminal of the comparison circuit;
a first capacitor one electrode of which is electrically connected to the inverting input terminal of the comparison circuit;
and
a second terminal electrically connected to the other electrode of the first capacitor,
wherein the first transistor comprises a metal oxide comprising indium in a channel formation region,
wherein the first terminal included in a k-th cell-balance circuit is electrically connected to the second terminal included in a (k−1)th cell-balance circuit,
wherein k is an integer greater than or equal to 3 and less than or equal to n,
wherein the first terminal included in the (k−1)th cell-balance circuit is electrically connected to the second terminal included in a (k−2)th cell-balance circuit, and
wherein a positive electrode of the secondary battery electrically connected to the k-th cell-balance circuit is electrically connected to the first terminal of the k-th cell-balance circuit, and a negative electrode thereof is electrically connected to the second terminal of the k-th cell-balance circuit.

12 more elements

A method of operating a semiconductor device, the semiconductor device comprising a first comparison circuit, a first transistor, a first capacitor, a first terminal, a second terminal, and a third terminal,

wherein the first terminal is electrically connected to a non-inverting input terminal of the first comparison circuit,
wherein one of a source and a drain of the first transistor and one electrode of the first capacitor are electrically connected to an inverting input terminal of the first comparison circuit,
wherein the second terminal is electrically connected to the other electrode of the first capacitor,
wherein the third terminal is electrically connected to the other of the source and the drain of the first transistor,
wherein the first transistor comprises a metal oxide in a channel formation region,
wherein the metal oxide comprises indium,
wherein a positive electrode terminal of a secondary battery is electrically connected to the first terminal,
wherein a negative electrode terminal of the secondary battery is electrically connected to the second terminal,
wherein the method comprises:
a first step of supplying a high-potential signal to a gate of the first transistor,
a second step of supplying a first signal to the third terminal,
a third step of supplying a second signal in accordance with the first signal to the inverting input terminal of the first comparison circuit,
a fourth step of supplying a low-potential signal to a gate of the first transistor,
a fifth step of outputting a low-potential signal from an output terminal of the first comparison circuit, and
a sixth step of reducing a current of the secondary battery by changing a signal from the output terminal of the first comparison circuit from the low-potential signal to the high-potential signal,
wherein the first signal is the sum of a voltage of the second terminal and a voltage A, and
wherein the voltage A is greater than or equal to 3 V and less than or equal to 5 V.

14 more elements

A semiconductor device comprising:

a first comparison circuit;
a second comparison circuit;
a third comparison circuit, a control circuit;
and
a secondary battery,
wherein the first comparison circuit, the second comparison circuit, and the third comparison circuit are configured to supply a signal to the control circuit,
wherein the control circuit is configured to control a charge current for the secondary battery in accordance with a signal supplied from the first comparison circuit,
wherein the control circuit is configured to stop charge of the secondary battery in accordance with a signal supplied from the second comparison circuit,
wherein the control circuit is configured to control an upper charge voltage limit of the secondary battery in accordance with a signal supplied from the third comparison circuit,
wherein the first comparison circuit is configured to compare a potential of a positive electrode of the secondary battery with a first reference potential,
wherein the second comparison circuit is configured to compare the potential of the positive electrode of the secondary battery with a second reference potential, and
wherein the third comparison circuit is configured to compare an ambient temperature with a third reference potential.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/269,330Filed 21 Aug 2019
Priority: JP 2018-16316831 Aug 2018
Published: 5 Aug 2021
Term ends: Not estimatedThe source records don’t support an estimate.

Classification18 codes

H02J 7/52
Acting upon multiple batteries simultaneously or sequentially: for charge balancing, e.g. equalisation of charge between batteries
H02J 7/54
For charge balancing, e.g. equalisation of charge between batteries: passive balancing, e.g. using resistors or parallel MOSFETs
H01M 10/425
Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells: structural combination with electronic…
H01M 10/441
Methods for charging or discharging: for several batteries or cells simultaneously or sequentially

Family

US 12,431,719 B2Related patent
US 2021/0242690 A1This patent

From the US filing history. Foreign family members aren’t listed.

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