Bottom electrode structure in memory device

An integrated chip, comprising:

• a bottom electrode disposed over a substrate and comprising a material having a first electronegativity, wherein the bottom electrode is disposed directly over a first interconnect that is a closest underlying interconnect to the bottom electrode;
• a top electrode over the bottom electrode;
• a data storage layer between the bottom electrode and the top electrode;
• and
• a reactivity reducing layer between the first interconnect and the bottom electrode and also between the data storage layer and the substrate, wherein the reactivity reducing layer has a second electronegativity that is greater than or equal to the first electronegativity.

An integrated chip, comprising:

• a lower interconnect arranged within an inter-level dielectric (ILD) structure over a substrate;
• a bottom electrode disposed over the lower interconnect, wherein a lower surface of the bottom electrode comprises a first material having a first electronegativity;
• a data storage layer comprising a metal and oxygen, the data storage layer arranged along an upper surface of the bottom electrode that faces away the substrate;
• a top electrode arranged over an upper surface of the data storage layer facing away from the substrate;
• and
• a reactivity reducing layer arranged between the lower surface of the bottom electrode and the lower interconnect, wherein the reactivity reducing layer has a second electronegativity that is greater than or equal to the first electronegativity.