Top electrode via with low contact resistance

An integrated chip, comprising:

• a memory device disposed over a substrate, the memory device comprising a data storage structure disposed between a bottom electrode and a multi-layer top electrode;
• a top electrode via disposed over and electrically coupled to the multi-layer top electrode;
• wherein the multi-layer top electrode comprises a first top electrode layer disposed over the data storage structure, and a second top electrode layer on the first top electrode layer and comprising a different material than the first top electrode layer;
• and
• wherein the second top electrode layer has a larger corrosion potential than the first top electrode layer.

A method of forming a memory device, comprising:

• forming a data storage layer on a bottom electrode layer over a substrate;
• forming a first top electrode layer over the data storage layer and a second top electrode layer over the first top electrode layer, wherein the first top electrode layer has a smaller corrosion potential than the second top electrode layer;
• performing a first patterning process on the first top electrode layer and the second top electrode layer to define a multi-layer top electrode;
• and
• performing a second patterning process on the data storage layer and the bottom electrode layer to define a data storage structure and a bottom electrode.