Intercalated metal/dielectric structure for nonvolatile memory devices

An integrated chip, comprising:

• an interconnect structure including a lower metal layer and an upper metal layer which are separated from one another by a first inter-level dielectric (ILD) layer;
• a bottom electrode disposed over the lower metal layer;
• a top electrode disposed over the bottom electrode, the top electrode residing below the upper metal layer;
• a plurality of metal layers and a plurality of dielectric layers stacked in alternating fashion over one another and sandwiched between the top electrode and the bottom electrode;
• an interlayer dielectric along outer sidewalls of the top electrode and along outer sidewalls of the plurality of metal layers and the plurality of dielectric layers;
• and
• a dielectric liner separating the outer sidewalls of the top electrode from the interlayer dielectric and extending continuously downward along outer sidewalls of the plurality of metal layers and the plurality of dielectric layers to separate the outer sidewalls of the plurality of metal layers and the plurality of dielectric layers from the interlayer dielectric.

An integrated chip, comprising:

• a lower interconnect structure within a first inter-level dielectric (ILD) layer over a substrate;
• a bottom electrode disposed over the lower interconnect structure;
• an upper electrode disposed over the bottom electrode;
• and
• an intercalated metal/dielectric structure sandwiched between the bottom electrode and the upper electrode, the intercalated metal/dielectric structure comprising a lower dielectric layer over the bottom electrode, an upper dielectric layer over the lower dielectric layer, and a first metal layer separating the upper dielectric layer from the lower dielectric layer.