Microstructure enhanced absorption photosensitive devices

An integrated, single-chip structure comprising:

• I-regions of low-doped or undoped first semiconductor material that are laterally spaced from each other by deliberately formed first holes extending in said first semiconductor material;
• regions of said first semiconductor material doped to one polarity;
• and
• regions of a second semiconductor material that is different from said first semiconductor material and comprise triplets each formed of a region that is doped to an opposite polarity and is laterally between regions doped to said one polarity;
• wherein adjacent regions of said first semiconductor material are laterally spaced from each other by said triplets of the second semiconductor material;
• wherein said I-regions and regions of said first semiconductor material doped to said one polarity and said regions of said second semiconductor material doped to an opposite polarity are configured as photodetectors generating electrical signals in response to illumination, where illumination concurrently illuminating plural ones of said holes contributes to a respective single one of said electrical signal;
• and
• wherein said regions of said second semiconductor material are configured as avalanche structures.

An integrated, single-chip structure comprising:

• an I-region of low-doped or undoped Si semiconductor material;
• P-doped regions and N-doped regions extending in said semiconductor material;
• deliberately formed holes extending into said semiconductor material and laterally spacing said doped regions;
• wherein each P-doped region is laterally spaced from an adjacent N-doped region by at least one of said holes;
• and
• first and second interdigitated electrodes, respectively coupled to said P-doped regions to said N-doped regions;
• and
• wherein said structure is configured to generate an electrical signal in response to light concurrently impinging on a plurality of said holes to generate a respective common electrical output representing said light and to operate at Gigahertz data rates.

An integrated, single-chip structure comprising:

• a first I-region of low-doped or undoped Ge or Ge/Si alloy semiconductor material;
• a second I-region of low-doped or undoped Si semiconductor material;
• doped regions in said Ge or Ge/Si material that are doped to one polarity;
• doped regions in said Si semiconductor material that are doped to opposite polarity and laterally space from each other said regions doped to said one polarity;
• holes deliberately formed in said Ge or GeSi alloy material;
• and
• first and second interdigitated electrodes coupled respectively to said P-doped regions and to said N-doped regions;
• and
• wherein said structure is configured to generate electrical signals in response to light and to operate at Gigahertz data rates.

An integrated, single-chip structure comprising:

• an I-region of low-doped or undoped Ge or GeSi alloy semiconductor material;
• P-doped regions and N-doped regions extending in said semiconductor material;
• deliberately formed holes extending into said semiconductor material and laterally spacing said doped regions from each other;
• wherein each P-doped region is laterally spaced from an adjacent N-doped region by at least one of said holes;
• a low-doped Si region extending along said Ge or GeSi region at a side thereof opposite said doped regions;
• and
• first and second interdigitated electrodes coupled respectively to said regions doped to one conductivity and to said regions doped to opposite conductivity;
• and
• wherein said structure is configured to generate electrical signals in response to light and to operate at Gigahertz data rates

An integrated, single-chip structure comprising:

• I-regions of Si semiconductor that are low-doped or undoped;
• first regions of said Si semiconductor material doped to one polarity;
• and
• second regions of said Si semiconductor material doped to opposite polarity and third regions of said Si semiconductor material doped to said one polarity, said second a third regions forming triplets each comprising one of said second regions doped to opposite polarity and located laterally between two of said second regions doped to said one polarity;
• wherein adjacent ones of said first regions are laterally spaced from each other by at least one or said triplets;
• deliberately formed holes extending into said I-regions, wherein a plurality of said holes is laterally between each adjacent pair of one of said first regions and one of said triplets;
• wherein said I-regions and said second regions are configured as photodetectors generating electrical signals in response to illumination, and said triplets are configured as avalanche structures.

An integrated, single-chip structure comprising a photosensitive portion at one side of a substrate and an active CMOS or BICMOS electronic circuit that is at an opposite side of the substrate, wherein:

• said photosensitive portion at one side or of said substrate comprises plural sets of regions, each set comprising a P-doped region, an N-doped region, and an I-region of low doped or undoped semiconductor material that is between the N-doped region and the P-doped region;
• plural holes extend in said photosensitive regions and are laterally located between said sets;
• said active circuit at an opposite side of said substrate comprises plural active electronic elements;
• first and second electrodes connect respectively said P-doped regions and said N-doped regions and are configured to carry electrical signals generated by said photosensitive portion in response to illumination to said active electronic circuit for processing;
• wherein at least two of said sets are connected to combine the electrical signals they generate into a common signal;
• and
• output electrodes are connected to said active electronic circuit and are configured to deliver electrical signals processed by the active electronic circuit.