US 2021/0242351 A1 · EFFICIENT THREE-DIMENSIONAL DESIGN FOR LOGIC APPLICATIONS USING VARIABLE VOLTAGE THRESHOLD THREE-DIMENSIONAL CMOS DEVICES

Abstract

A charge trap field-effect transistor (FET) includes multiple layers of dielectric material defining a charge trapping layer. A p-doped (or n-doped) source region and a p-doped (or n-doped) drain region are connected via a nano-channel, the nano-channel being formed between the multiple layers of dielectric, thus forming a charge trap FET. A charge trap complimentary current field-effect transistor (CFET) includes multiple layers of dielectric material defining a charge trapping layer and includes a 3D charge trap PFET formed with p+ symmetrical source/drain region formed over a 3D charge trap NFET formed with n+ symmetrical source/drain region.

Claims20

Dependent claims

A semiconductor device comprising:
a stack of field-effect transistors (FETs) formed on a substrate, the stack extending perpendicular to a surface of the substrate, each FET in the stack of FETs including one nano-channel that connects one source/drain region on a first side of the FET with another source/drain region on an opposite side of the FET, wherein at least one dielectric layer is formed around the nano-channel, the at least one dielectric layer forming a charge trapping layer.

Dependencies are inferred from the claim text.

Efficient three-dimensional design for logic applications using variable voltage threshold three-dimensional cmos devices

Life of this patent

Efficient three-dimensional design for logic applications using variable voltage threshold three-dimensional cmos devices

Life of this patent

Abstract

Claims20