Process and structure for a superjunction device

A method of forming a superjunction device structure, comprising:

• depositing an epitaxial N-type layer over an N-type substrate;
• depositing a hard mask layer over the epitaxial N-type layer;
• etching a trench with a sloped angle on the epitaxial N-type layer;
• forming a first vertical column adjacent to the trench by implantation and diffusion;
• forming a second vertical column adjacent to the first vertical column by implantation and diffusion;
• filling the trench with an insulating material such that a formation of key-holes is avoided;
• performing a chemical-mechanical planarization (CMP) to remove the insulating material over the first and second vertical column and the epitaxial N-type layer;
• depositing a gate oxide and a polysilicon layer;
• etching the gate oxide and the polysilicon layer with a gate mask above the polysilicon layer to form a gate;
• implanting a source contact below the gate oxide;
• implanting a P-body region below the source contact;
• forming a source electrode and a gate contacts;
• and
• forming a drain contact below the N-type substrate.