Barrier structure configured to increase performance of iii-v devices

An integrated chip, comprising:

• a buffer layer overlying a substrate;
• an undoped binary III-V semiconductor layer overlying the buffer layer;
• a doped binary III-V semiconductor layer overlying the undoped binary III-V semiconductor layer, wherein the doped binary III-V semiconductor layer is disposed within a middle region of the substrate;
• and
• a barrier structure overlying the undoped binary III-V semiconductor layer, wherein the barrier structure comprises a III-V semiconductor material with a first element, wherein an atomic concentration of the first element discretely increases along a first direction that extends from the middle region to a peripheral region, where the peripheral region laterally surrounds the middle region, and wherein the first direction points away from the doped binary III-V semiconductor layer.

A method of forming an integrated chip, comprising:

• depositing an undoped layer over a substrate;
• depositing a first barrier layer over the undoped layer, wherein the first barrier layer comprises a III-V semiconductor material with a first atomic percentage of a first element;
• forming a doped layer over the first barrier layer;
• selectively forming a second barrier layer over the first barrier layer such that the second barrier layer is laterally offset from a perimeter of the doped layer by a non-zero distance, wherein the second barrier layer comprises the III-V semiconductor material with a second atomic percentage of the first element, wherein the second atomic percentage is greater than the first atomic percentage;
• and
• forming a gate electrode over the doped layer.