Isolation structures of semiconductor devices

A field effect transistor (FET) structure, comprising:

• a substrate;
• a first vertical structure and a second vertical structure formed over the substrate, wherein
• each of the first and second vertical structures comprises a channel layer;
• a gate structure disposed over portions of the first and second vertical structures;
• and
• an isolation structure disposed between the first and second vertical structures and comprising a first sidewall, a second sidewall, and a footing region vertically between the first sidewall and the second sidewall, wherein:
• the first sidewall and second sidewalls are between a top surface and a bottom surface of the isolation structure;
• and
• the footing region is tapered from the second sidewall to the first sidewall.

A method for forming a semiconductor structure, comprising:

• forming a first fin structure and a second fin structure over a substrate;
• forming an isolation structure laterally between the first and second fin structures, wherein the isolation structure comprises a first insulating layer and a second insulating layer disposed over the first insulating layer;
• and
• removing a portion of the isolation structure to form a footing region tapering from a sidewall of the isolation structure to a top surface of the isolation structure.