Vertical conduction electronic power device having a reduced on resistance and manufacturing process thereof

A method for manufacturing a vertical conduction electronic power device, comprising:

• forming a plurality of insulated-gate regions on a wafer of semiconductor material, the wafer including an epitaxial layer and a substrate and having a first and a second surface, the plurality of insulated-gate regions formed on the first surface of the wafer or within the epitaxial layer;
• forming a first and a second conduction region within the epitaxial layer;
• and
• forming, in the substrate, at least one silicide region, which extends starting from the second surface of the body towards the epitaxial layer.

A device, comprising:

• a substrate including a silicide layer;
• an epitaxial layer of semiconductor material on the silicide layer, the epitaxial layer including:
• a drift region on and in contact with the silicide layer, the drift region having a first doping type;
• an active region on the drift region, the active region having a second doping type that is different from the first doping type;
• and
• a source region on the active region, the source region having the first doping type and having a higher concentration of the first doping type than the drift region;
• and
• first and second insulated-gate regions extending into the drift region from a surface of the epitaxial layer, the active region and the source region disposed between and abutting the first and second insulated-gate regions.