US 2021/0242241 A1 · THREE-DIMENSIONAL NOR ARRAY INCLUDING VERTICAL WORD LINES AND DISCRETE MEMORY ELEMENTS AND METHODS OF MANUFACTURE

Abstract

A three-dimensional memory device includes an alternating stack of source layers and drain layers located over a substrate, a memory opening vertically extending through the alternating stack, a vertical word line located in the memory opening and vertically extending through each of the source layers and the drain layers of the alternating stack, discrete semiconductor channels contacting horizontal surfaces of a respective vertically neighboring pair of a source layer of the source layers and a drain layer of the drain layers, and a vertical stack of discrete memory material portions laterally surrounding the vertical word line.

Claims20

Dependent claims

A three-dimensional memory device, comprising:

an alternating stack of source layers and drain layers located over a substrate;
a memory opening vertically extending through the alternating stack;
a vertical word line located in the memory opening and vertically extending through each of the source layers and the drain layers of the alternating stack;
discrete semiconductor channels contacting horizontal surfaces of a respective vertically neighboring pair of a source layer of the source layers and a drain layer of the drain layers;
and
a vertical stack of discrete memory material portions laterally surrounding the vertical word line.

3 more elements

A method of forming a three-dimensional memory device, comprising:

forming a vertical repetition of unit layer stacks over a substrate, wherein each of the unit layer stacks comprises a source-level material layer, a sacrificial channel-level spacer layer, a drain-level material layer, and an inter-transistor-level insulating layer, wherein the source-level material layers are formed as, or are subsequently replaced with, source layers comprising at least one source-side conductive material, and the drain-level material layers are formed as, or are subsequently replaced with, drain layers comprising at least one drain-side conductive material;
forming memory openings vertically extending through the vertical repetition;
forming a vertical stack of annular recess cavities around each of the memory openings by laterally recessing the sacrificial channel-level spacer layers relative to the source-level material layers, the drain-level material layers, and the inter-transistor-level insulating layers;
forming at least one semiconductor oxide spacer over the source-level material layers and the drain-level material layers;
forming a vertical stack of memory material portions in the vertical stacks of annular recess cavities;
forming a vertical word line in each of the memory openings;
forming a backside trench through the vertical repetition;
and
replacing each of the sacrificial channel-level spacer layers with a respective semiconductor channel layer through the backside trench.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application

17/237,447Filed 22 Apr 2021

Priority

27 Dec 2019

Published

5 Aug 2021

Term ends

Not estimatedThe source records don’t support an estimate.

Classification17 codes

H10B 51/20
Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors: characterised by the three-dimensional [3D] arrangements, e.g. with…
H10D 64/035
Of data-storage electrodes: comprising conductor-insulator-conductor-insulator-semiconductor structures
H10B 41/10
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the top-view layout
H10B 41/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels

Three-dimensional nor array including vertical word lines and discrete memory elements and methods of manufacture

Life of this patent

Three-dimensional nor array including vertical word lines and discrete memory elements and methods of manufacture

Life of this patent

Abstract

Claims20