Semiconductor memory structure and device
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYU-MING LIN, CHUN-CHIEH LU, BO-FENG YOUNG, HAN-JONG CHIA, CHENCHEN JACOB WANG, SAI-HOOI YEONG
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Abstract
A semiconductor memory structure includes a semiconductor layer, a conductive layer disposed over the semiconductor layer, a gate penetrating through the conductive layer and the semiconductor layer, and an interposing layer disposed between the gate and the conductive layer and between the gate and the semiconductor layer, wherein a pair of channel regions is formed in the semiconductor layer at two sides of the gate.
Claims20
A semiconductor memory structure, comprising:
- a semiconductor layer;
- a conductive layer disposed over the semiconductor layer;
- a gate penetrating through the conductive layer and the semiconductor layer;
- and
- an interposing layer disposed between the gate and the conductive layer and between the gate and the semiconductor layer,
- wherein a pair of channel regions is formed in the semiconductor layer at two sides of the gate.
A semiconductor memory structure, comprising:
- a stack of alternating insulating layers, semiconductor layers and conductive layers;
- a plurality of gates arranged in an array configuration of rows and columns, and penetrating through the stack;
- and
- an interposing layer surrounding each of the gates,
- wherein a pair of channel regions is formed in the semiconductor layers at two sides of each of the gates.
A semiconductor memory structure comprising a stack of alternating insulating layers, semiconductor layers and conductive layers, the stack comprising:
- a memory array region comprising:
- a plurality of gates arranged in an array configuration of rows and columns and penetrating through the stack;
- an interposing layer surrounding each of the gates;
- and
- a plurality of word line connectors disposed on the gates;
- a plurality of first connection regions adjoined to the memory array region, extending along a column direction and configured in a staircase structure, each of the first connection regions comprising:
- a plurality of stepped surfaces of the conductive layers;
- and
- a plurality of bit line connectors disposed on the stepped surfaces of the conductive layers;
- and
- a plurality of second connection regions spaced apart from the first connection regions, adjoined to the memory array region, extending along the column direction and configured in a staircase structure, each of the second connection regions comprising:
- a plurality of stepped surfaces of the conductive layers;
- and
- a plurality of source line connectors disposed on the stepped surfaces of the conductive layers.
Dependencies are inferred from the claim text.