Three-dimensional semiconductor memory device

A three-dimensional semiconductor memory device comprising:

• a bottom substrate;
• a peripheral logic structure on the bottom substrate;
• a top substrate including a first conductive pattern, a second conductive pattern, and a third conductive pattern sequentially stacked on the peripheral logic structure;
• an electrode structure including gate electrodes stacked on the top substrate;
• vertical holes passing through the electrode structure, the third conductive pattern and the second conductive pattern;
• vertical semiconductor patterns in the vertical holes, respectively;
• and
• a data storage pattern between each of the vertical semiconductor patterns and the electrode structure,
• wherein bottom surfaces of the vertical holes are lower than a bottom surface of the first conductive pattern,
• wherein the data storage pattern includes a tunnel insulation layer, a blocking layer, and a charge storage layer between the tunnel insulation layer and the blocking layer,
• wherein the second conductive pattern is connected to the vertical semiconductor patterns.

A three-dimensional semiconductor memory device comprising:

• a bottom substrate;
• a peripheral logic structure on the bottom substrate;
• a top substrate including a first conductive pattern, a second conductive pattern, and a third conductive pattern sequentially stacked on the peripheral logic structure;
• an electrode structure including gate electrodes stacked on the top substrate;
• vertical holes passing through the electrode structure, the third conductive pattern and the second conductive pattern;
• vertical semiconductor patterns in the vertical holes, respectively;
• and
• a data storage pattern between each of the vertical semiconductor patterns and the electrode structure,
• wherein bottom surfaces of the vertical holes are lower than a bottom surface of the first conductive pattern,
• wherein the data storage pattern includes a tunnel insulation layer, a blocking layer, and a charge storage layer between the tunnel insulation layer and the blocking layer.