Three-dimensional semiconductor memory devices

A three-dimensional (3D) semiconductor memory device comprising:

• a peripheral logic structure on a semiconductor substrate;
• a horizontal semiconductor layer on the peripheral logic structure, the horizontal semiconductor layer comprising a cell array region and a connection region electrically connected to the cell array region;
• electrode structures comprising a plurality of electrodes stacked on the horizontal semiconductor layer in the cell array region and the connection region, the electrode structures extending in a first direction and being spaced apart from each other by separation regions in a second direction perpendicular to the first direction;
• at least one contact region comprising a through wiring structure electrically connecting the electrode structures to the peripheral logic structure in the connection region;
• and
• ground select gate electrodes comprising lowermost electrodes among the plurality of electrodes of the electrode structures in the cell array region and the connection region,
• wherein the separation regions comprise a first end portion on a level of the ground select gate electrodes, and
• wherein at least one ground select gate cutting region overlaps the first end portion of the separation regions and electrically isolates the ground select gate electrodes from each other.

A three-dimensional (3D) semiconductor memory device comprising:

• a peripheral logic structure on a semiconductor substrate;
• a horizontal semiconductor layer on the peripheral logic structure, the horizontal semiconductor layer comprising a cell array region and a connection region electrically connected to the cell array region;
• electrode structures comprising a plurality of electrodes stacked on the horizontal semiconductor layer in the cell array region and the connection region, the electrode structures each extending in a first direction and being spaced apart from each other by at least one separation region in a second direction perpendicular to the first direction;
• at least one contact region comprising a through wiring structure electrically connecting the electrode structures to the peripheral logic structure in the connection region;
• and
• ground select gate electrodes comprising lowermost electrodes among the plurality of electrodes of the electrode structures in the cell array region and the connection region,
• wherein the at least one separation region comprises a first end portion on a level of the ground select gate electrodes, and
• wherein at least one ground select gate cutting region overlaps the first end portion of the at least one separation region and electrically isolates the ground select gate electrodes from each other.