Semiconductor memory device and manufacturing method thereof

A semiconductor memory device comprising:

• a peripheral transistor;
• a first insulating layer covering the peripheral transistor;
• a source layer on the first insulating layer;
• a stack structure on the source layer;
• and
• a peripheral contact structure penetrating the stack structure and the source layer, the peripheral contact structure being electrically connected to the peripheral transistor,
• wherein the stack structure includes alternately stacked insulating patterns and conductive patterns,
• wherein the peripheral contact structure is in contact with the conductive patterns, and
• wherein a level of an uppermost portion of the peripheral contact structure is higher than a level of an uppermost conductive pattern among the conductive patterns.