Charge trap memory devices

A semiconductor memory cell, comprising:

• a Metal-Oxide-Semiconductor Filed-Effect Transistor (MOSFET) comprising a substrate, a gate structure, a high-k dielectric material under the gate structure, a source region and a drain region;
• and
• a self-heating circuit is configured to apply a bias to the substrate, the high-k dielectric metal gate structure, the source region and the drain region,
• wherein the high-k dielectric of the high-k dielectric metal gate structure releases a trapped charge when a bias direction applied to the MOSFET is alternated between the source region and the drain region.