US 2021/0242229 A1Published application

Three-dimensional semiconductor device

AssigneeSamsung Electronics Co., Ltd.

InventorsBYOUNG IL LEE, Yu Jin Seo, Jun Eon Jin

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Abstract

A three-dimensional semiconductor device includes first and second extended regions disposed on a substrate spaced apart from each other, a memory block disposed on the substrate between the first and second extended regions, and first and second main separation structures disposed on the substrate spaced apart from each other. The first extended region, the memory block and the second extended region are disposed between the first and second main separation structures. The memory block includes data storage regions and word lines. The word lines extend from the memory block and pass through the first and second extended regions. A distance between the first and second main separation structures located on both sides of the first extended region is greater than a distance between the first and second main separation structures located on both sides of the memory block.

Claims20

Dependent claims

A semiconductor device comprising:

a lower structure;
a first main separation structure and a second main separation structure spaced apart from each other and on the lower structure;
a stacked structure between the first main separation structure and the second main separation structure, and including a memory array region and an extended region;
vertical structures penetrating through the memory array region of the stacked structure;
first auxiliary separation structures penetrating through a first region of the extended region of the stacked structure, between the first main separation structure and the second main separation structure, and sequentially arranged in a first direction parallel to an upper surface of the lower structure;
and
second auxiliary separation structures penetrating through a second region of the extended region of the stacked structure, between the first main separation structure and second main separation structure, and sequentially arranged in the first direction;
wherein each of the first and second auxiliary separation structures has a linear shape extending in a second direction perpendicular to the first direction,
wherein the stacked structure includes word lines and string selection lines on the word lines,
wherein a number of the string selection lines at a first height level is N,
wherein a number of the second auxiliary separation structures sequentially arranged in the first direction is N−2, and
wherein N is an integer greater than three (3).

9 more elements

A semiconductor device comprising:

a lower structure;
a first main separation structure and a second main separation structure spaced apart from each other and on the lower structure;
a stacked structure between the first main separation structure and the second main separation structure, and including a memory array region and an extended region;
vertical structures penetrating through the memory array region of the stacked structure;
first auxiliary separation structures penetrating through a first region of the extended region of the stacked structure, between the first main separation structure and the second main separation structure, and sequentially arranged in a first direction parallel to an upper surface of the lower structure;
and
second auxiliary separation structures penetrating through a second region of the extended region of the stacked structure, between the first main separation structure and second main separation structure, and sequentially arranged in the first direction;
wherein each of the first and second auxiliary separation structures has a linear shape extending in a second direction perpendicular to the first direction,
wherein the stacked structure includes gate electrodes stacked in the memory array region and extended to the extended region,
wherein the gate electrodes include first gate electrodes including first gate pads arranged in a first stepped shape in the first region of the extended region and second gate electrodes including second gate pads arranged in a second stepped shape in the second region of the extended region,
wherein the first gate electrodes are at a higher level than the second gate electrodes,
wherein the second stepped shape is different from the first stepped shape, and
wherein the first auxiliary separation structures are not aligned with the second auxiliary separation structures in the second direction in a plan view.

10 more elements

A semiconductor device comprising:

a lower structure;
a first main separation structure and a second main separation structure spaced apart from each other and on the lower structure;
a stacked structure between the first main separation structure and the second main separation structure, and including a memory array region and an extended region;
vertical structures penetrating through the memory array region of the stacked structure;
first auxiliary separation structures penetrating through a first region of the extended region of the stacked structure, between the first main separation structure and the second main separation structure, and sequentially arranged in a first direction parallel to an upper surface of the lower structure;
and
second auxiliary separation structures penetrating through a second region of the extended region of the stacked structure, between the first main separation structure and second main separation structure, and sequentially arranged in the first direction;
wherein each of the first and second auxiliary separation structures has a linear shape extending in a second direction perpendicular to the first direction,
wherein the stacked structure includes word lines and string selection lines on the word lines,
wherein at least one of the first and second main separation structures includes a first linear portion adjacent to the memory array region and the first region of the extended region, a second linear portion adjacent to the second region of the extended region and a bent portion between the first linear portion and the second linear portion,
wherein each of the first linear portion and the second linear portion has a linear shape extending in the second direction.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/218,267Filed 31 Mar 2021
Priority: KR 10-2018-005730618 May 2018
Published: 5 Aug 2021
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

H10B 43/10
EEPROM devices comprising charge-trapping gate insulators: characterised by the top-view layout
H10B 41/10
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the top-view layout
H10B 41/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35
Characterised by the memory core region: with a cell select transistor, e.g. NAND

Family

Application16/227,985Continuation · filed 20 Dec 2018
Application17/218,267Continuation
US 10,978,465 B2Related patent
US 11,812,609 B2Related patent
US 2019/0355737 A1Published application
US 2021/0242229 A1This patent

From the US filing history. Foreign family members aren’t listed.

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