3d memory semiconductor devices and structures
AssigneeMonolithic 3D Inc.
InventorsZvi Or-Bach, Jin-Woo Han, Eli Lusky
Life of this patent
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Abstract
A 3D memory device, the device including: a plurality of memory cells, where each of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain and a channel; a plurality of bit-line pillars, where each of the plurality of bit-line pillars is directly connected to a plurality of the source or the drain, where the bit-line pillars are vertically oriented, where the channel is horizontally oriented, and where the channel includes a circular shape or an ellipsoidal shape.
Claims20
A 3D memory device, the device comprising:
- a plurality of memory cells,
- wherein each of said plurality of memory cells comprises at least one memory transistor,
- wherein each of said at least one memory transistor comprises a source, a drain and a channel;
- a plurality of bit-line pillars,
- wherein each of said plurality of bit-line pillars is directly connected to a plurality of said source or said drain,
- wherein said bit-line pillars are vertically oriented,
- wherein said channel is horizontally oriented, and
- wherein said channel comprises a circular shape or an ellipsoidal shape.
A 3D memory device, the device comprising:
- a plurality of memory cells,
- wherein each of said plurality of memory cells comprises at least one memory transistor,
- wherein each of said at least one memory transistor comprises a source, a drain and a channel;
- a plurality of bit-line pillars,
- wherein each of said plurality of bit-line pillars is directly connected to a plurality of said source or said drain,
- wherein said bit-line pillars are vertically oriented, and
- wherein said channel is horizontally oriented and comprises a channel width longer than 5 nm and shorter than 25 nm.
A 3D memory device, the device comprising:
- a plurality of memory cells,
- wherein each of said plurality of memory cells comprises at least one memory transistor,
- wherein each of said at least one memory transistor comprises a source, a drain and a channel;
- a plurality of bit-line pillars,
- wherein each of said plurality of bit-line pillars is directly connected to a plurality of said source or said drain,
- wherein said bit-line pillars are vertically oriented,
- wherein at least one of said plurality of said memory cells comprise a tunneling oxide thinner than 1 nm, and
- wherein at least one of said plurality of said memory cells comprise a tunneling oxide thicker than 3 nm.
Dependencies are inferred from the claim text.