Memory Arrays Comprising Vertically-Alternating Tiers Of Insulative Material And Memory Cells And Methods Of Forming A Memory Array Comprising Memory Cells Individually Comprising A Transistor And A Capacitor

A memory array comprising vertically-alternating tiers of insulative material and memory cells, the memory cells individually comprising:

• a transistor comprising first and second source/drain regions having a channel region there-between, at least a portion of the channel region being horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions;
• and
• a capacitor comprising first and second electrodes having a capacitor insulator there-between, the first electrode being electrically coupled to the first source/drain region, the second capacitor electrodes of multiple of the capacitors in the array being electrically coupled with one another;
• a pair of laterally-spaced access-line pillars extending elevationally through the vertically-alternating tiers on opposite sides of individual of the channel regions that are in different of the memory-cell tiers, portions of the access-line pillars in the different memory-cell tiers comprising a pair of gates on the opposite sides of the individual channel regions of individual of the transistors in the different memory-cell tiers;
• and
• a sense line electrically coupled to multiple of the second source/drain regions.

A method of forming a memory array, the memory array comprising memory cells individually comprising a transistor and a capacitor, the method comprising:

• forming vertically-alternating tiers of insulative material and transistor material;
• the transistor-material tiers individually comprising a first source/drain region and a second source/drain region having a channel region horizontally there-between;
• forming a pair of access-line pillars extending elevationally through the vertically-alternating tiers on opposite sides of individual of the channel regions that are in different of the transistor-material tiers, portions of the access-line pillars in the different transistor-material tiers comprising a pair of gates on the opposite sides of the individual channel regions of individual of the transistors in the different transistor-material tiers;
• forming a sense line electrically coupled to multiple of the second source/drain regions;
• and
• forming capacitors individually comprising first and second electrodes having a capacitor insulator there-between, the first electrode being electrically coupled to individual of the first source/drain regions, the second capacitor electrodes of multiple of the capacitors in the array being electrically coupled with one another.