Semiconductor memory device and manufacturing method thereof

A semiconductor memory device, comprising:

• a first peripheral transistor;
• a first insulating layer covering the first peripheral transistor;
• a cell source structure on the first insulating layer;
• a first stack structure disposed on the cell source structure, the first stack structure including first insulating patterns and conductive patterns, which are alternately stacked;
• a channel structure penetrating the first stack structure, the channel structure being connected to the cell source structure;
• and
• a second peripheral transistor on the first insulating layer,
• wherein the first peripheral transistor is disposed at a level lower than that of the cell source structure, and
• the second peripheral transistor is disposed at the same level as the cell source structure.