Controlling trap formation to improve memory window in one-time prograrm devices

A one-time program (OTP) memory cell, comprising:

• a read transistor coupled in series with a program transistor over a substrate;
• wherein the read transistor comprises a read dielectric layer arranged between a read gate electrode and the substrate;
• wherein the program transistor comprises a program dielectric layer arranged between a program gate electrode and the substrate;
• wherein the read dielectric layer has a first average surface roughness;
• and
• wherein the program dielectric layer has a second average surface roughness that is greater than the first average surface roughness.

A method of forming a one-time program (OTP) memory cell, the method comprising:

• forming a first dummy gate stack comprising a first dummy gate electrode over a program dielectric layer on a substrate;
• forming a second dummy gate stack comprising a second dummy gate electrode over a read dielectric layer on the substrate;
• forming a masking structure over the second dummy gate stack;
• performing a first etching process to remove the first dummy gate electrode to expose the program dielectric layer;
• removing the masking structure;
• performing a second etching process to remove the second dummy gate electrode to expose the read dielectric layer, wherein the program dielectric layer is exposed to the second etching process;
• and
• forming a program gate electrode over the program dielectric layer and a read gate electrode over the read dielectric layer.