US 2021/0242220 A1 · SEMICONDUCTOR DEVICE

Abstract

A highly integrated semiconductor device is provided. The semiconductor device includes a substrate, a prism-like insulator, a memory cell string including a plurality of transistors connected in series. The prism-like insulator is provided over the substrate. The memory cell string is provided on the side surface of the prism-like insulator. The plurality of transistors each include a gate insulator and a gate electrode. The gate insulator includes a first insulator, a second insulator, and a charge accumulation layer. The charge accumulation layer is positioned between the first insulator and the second insulator.

Claims9

Dependent claims

A semiconductor device comprising:

a substrate;
a plurality of transistors over the substrate,
wherein channel formation regions of the plurality of transistors are provided in a same oxide semiconductor,
wherein the plurality of transistors are provided in a direction perpendicular to the substrate, and
wherein the oxide semiconductor includes a plurality of c-axis aligned crystal parts.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application

17/236,115Filed 21 Apr 2021

Priority

JP 2015-10614526 May 2015

Published

5 Aug 2021

Term ends

Not estimatedThe source records don’t support an estimate.

Classification9 codes

H10B 43/35
Characterised by the memory core region: with cell select transistors, e.g. NAND
G11C 16/0466
Using variable threshold transistors, e.g. FAMOS: comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon…
G11C 16/0483
Using variable threshold transistors, e.g. FAMOS: comprising cells having several storage transistors connected in series
H10B 43/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels

Semiconductor device

Life of this patent

Semiconductor device

Life of this patent

Abstract

Claims9