Interconnect and memory structures having reduced topography variation formed in the beol

A structure comprising:

• at least one electrically conductive structure partially embedded in an interconnect dielectric material layer, wherein the interconnect dielectric material layer has a recessed surface located laterally adjacent to the at least one electrically conductive structure;
• a first dielectric capping layer located on the interconnect dielectric material layer and the at least one electrically conductive structure, wherein the first dielectric capping layer has a non-planar bottom surface that contacts both the recessed surface of the interconnect dielectric material layer and a planar topmost surface of the at least one electrically conductive structure;
• a second dielectric capping layer located on the first dielectric capping layer, wherein the second dielectric capping layer has an entirely planar topmost surface;
• and
• at least one metal-containing structure located in the first dielectric capping layer and the second dielectric capping layer, wherein the at least one metal-containing structure contacts the at least one electrically conductive structure.