US 2021/0242215 A1Published application

Methods of manufacturing semiconductor devices

AssigneeSamsung Electronics Co., Ltd.

InventorsHye Sung PARK, Jong Hyuk PARK, Jin Woo BAE, Bo Un YOON, Il Young YOON, Bong Sik CHOI

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Abstract

A method of manufacturing a semiconductor device includes forming a first pattern structure having a first opening and a second pattern structure having a second opening on a substrate, forming a gap fill layer in the second opening, forming fences and contact structures in the first opening, removing the gap fill layer in the second opening, forming an upper conductive layer to cover the first and second pattern structures, the fences, and the contact structures, forming a mask pattern based on a photolithography process using the second pattern structure covered by the upper conductive layer as an align mark, and etching the upper conductive layer using the mask pattern to form upper conductive patterns. A width of the second opening is larger than a width of a first opening. A thickness of the upper conductive layer is smaller than a depth of the second opening.

Claims20

Dependent claims

A semiconductor device, comprising:

a substrate including a first active region and a second active region, the first active region including a first impurity region and a second impurity region, the second active region including a third impurity region and a fourth impurity region;
a bit line structure electrically connected to the first impurity region of the first active region, the bit line structure including a bit line conductive pattern and a bit line capping pattern that is disposed on the bit line conductive pattern;
a gate structure disposed on the second active region and including a gate conductive pattern and a gate capping pattern that is disposed on the gate conductive pattern;
a first contact structure electrically connected to the second impurity region of the first active region and including a lower contact pattern and an upper contact pattern that is disposed on the lower contact pattern, the upper contact pattern including a first barrier layer and a first metal layer that is disposed on the first barrier layer;
a second contact structure electrically connected to the third impurity region or the fourth impurity region of the second active region, the second contact structure including a second barrier layer and a second metal layer that is disposed on the second barrier layer;
a first conductive pad disposed on the first contact structure;
and
a second conductive pad disposed on the second contact structure,
wherein the bit line capping pattern of the bit line structure includes a first bit line capping layer, a second bit line capping layer that is disposed on the first bit line capping layer, and a third bit line capping layer that is disposed on the second bit line capping layer,
wherein the gate capping pattern of the gate structure includes a first gate capping layer, a second gate capping layer that is disposed on the first gate capping layer, and a third gate capping layer that is disposed on the second gate capping layer,
wherein the first conductive pad contacts a top surface of the third bit line capping layer of the bit line capping pattern of the bit line structure,
wherein the top surface of the third bit line capping layer of the bit line capping pattern of the bit line structure is substantially coplanar with a top surface of the first barrier layer and a top surface of the first metal layer of the upper contact pattern of the first contact structure,
wherein the second conductive pad contacts a top surface of the third gate capping layer of the gate capping pattern of the gate structure, and
wherein the top surface of the third gate capping layer of the gate capping pattern of the gate structure is substantially coplanar with a top surface of the second barrier layer and a top surface of the second metal layer of the second contact structure.

11 more elements

A semiconductor device, comprising:

a substrate including a first active region and a second active region, the first active region including a first impurity region and a second impurity region, the second active region including a third impurity region and a fourth impurity region;
a bit line structure electrically connected to the first impurity region of the first active region, the bit line structure including a bit line conductive pattern and a bit line capping pattern that is disposed on the bit line conductive pattern;
a gate structure disposed on the second active region and including a gate conductive pattern and a gate capping pattern that is disposed on the gate conductive pattern;
a first contact structure electrically connected to the second impurity region of the first active region and including a lower contact pattern and an upper contact pattern that is disposed on the lower contact pattern;
a second contact structure electrically connected to the third impurity region or the fourth impurity region of the second active region;
a first conductive pad disposed on the first contact structure;
and
a second conductive pad disposed on the second contact structure,
wherein the bit line capping pattern of the bit line structure includes a first bit line capping layer, a second bit line capping layer that is disposed on the first bit line capping layer, and a third bit line capping layer that is disposed on the second bit line capping layer,
wherein the gate capping pattern of the gate structure includes a first gate capping layer, a second gate capping layer that is disposed on the first gate capping layer, and a third gate capping layer that is disposed on the second gate capping layer,
wherein a bottom surface of the first conductive pad contacts a top surface of the upper contact pattern of the first contact structure and a top surface of the third bit line capping layer of the bit line capping pattern of the bit line structure,
wherein a bottom surface of the second conductive pad contacts a top surface of the second contact structure and a top surface of the third gate capping layer of the gate capping pattern of the gate structure,
wherein the first bit line capping layer of the bit line capping pattern of the bit line structure includes a same material as the first gate capping layer of the gate capping pattern of the gate structure,
wherein the second bit line capping layer of the bit line capping pattern of the bit line structure includes a same material as the second gate capping layer of the gate capping pattern of the gate structure, and
wherein the third bit line capping layer of the bit line capping pattern of the bit line structure includes the same material as the third gate capping layer of the gate capping pattern of the gate structure.

12 more elements

A semiconductor device, comprising:

a substrate including a first active region and a second active region, the first active region including a first impurity region and a second impurity region, the second active region including a third impurity region and a fourth impurity region;
a bit line structure electrically connected to the first impurity region of the first active region, the bit line structure including a bit line conductive pattern and a bit line capping pattern that is disposed on the bit line conductive pattern;
a gate structure disposed on the second active region and including a gate conductive pattern and a gate capping pattern that is disposed on the gate conductive pattern;
a first contact structure electrically connected to the second impurity region of the first active region and including a lower contact pattern and an upper contact pattern that is disposed on the lower contact pattern, the upper contact pattern including a first barrier layer and a first metal layer that is disposed on the first barrier layer;
a second contact structure electrically connected to the third impurity region or the fourth impurity region of the second active region, the second contact structure including a second barrier layer and a second metal layer that is disposed on the second barrier layer;
a first conductive pad disposed on the upper contact pattern of the first contact structure;
a second conductive pad disposed on the second contact structure;
a first insulation pattern disposed on a side surface of the upper contact pattern of the first contact structure and a side surface of the first conductive pad;
a second insulation pattern disposed on a side surface of the second conductive pad;
and
an etch stop layer disposed on the first conductive pad, the first insulation pattern, the second conductive pad and the second insulation pattern,
wherein a top surface of the first conductive pad is substantially coplanar with a top surface of the first insulation pattern,
wherein a bottom surface of the first conductive pad contacts a top surface of the first barrier layer and a top surface of the first metal layer of the upper contact pattern of the first contact structure,
wherein a top surface of the second conductive pad is substantially coplanar with a top surface of the second insulation pattern, and
wherein a bottom surface of the second conductive pad contacts a top surface of the second barrier layer and a top surface of the second metal layer of the second contact structure.

12 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/237,195Filed 22 Apr 2021
Priority: KR 10-2019-000317610 Jan 2019
Published: 5 Aug 2021
Term ends: Not estimatedThe source records don’t support an estimate.

Classification13 codes

H10B 12/09
Manufacture or treatment: with simultaneous manufacture of the peripheral circuit region and memory cells
H10B 12/02
Manufacture or treatment: for one transistor one-capacitor [1T-1C] memory cells
H10B 12/315
Having a storage electrode stacked over the transistor: with the capacitor higher than a bit line
H10B 12/50
Dynamic random access memory [DRAM] devices: peripheral circuit region structures

Family

Application16/564,688Continuation · filed 9 Sep 2019
Application17/237,195Continuation
US 11,011,526 B2Related patent
US 11,581,318 B2Related patent
US 2020/0227315 A1Published application
US 2021/0242215 A1This patent

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