High-density 3d-dram cell with scaled capacitors

A semiconductor device, comprising:

• a semiconductor substrate;
• a bottom capacitor electrode disposed over the semiconductor substrate;
• a lower capacitor dielectric structure disposed over the bottom capacitor electrode;
• first and second lower source regions disposed over the lower capacitor dielectric structure and spaced laterally apart from one another;
• a lower channel region disposed directly over the first and second lower source regions;
• first and second lower drain regions directly over the lower channel region, wherein the lower channel region separates the first and second lower drain regions from the first and second lower source regions, respectively;
• a pair of gate dielectric regions extending upwards in a direction generally perpendicular to an upper surface of the semiconductor substrate and in parallel with one another, the pair of gate dielectric regions having inner sidewalls that laterally bound outer edges of the bottom capacitor electrode, that laterally bound outer edges of the first and second lower source regions, that laterally bound outer edges of the lower channel region, and that laterally bound outer edges of the first and second lower drain regions;
• and
• a pair of metal gates extending upward in parallel with the pair of gate dielectric regions, wherein the pair of metal gates have inner sidewalls that extend along outer sidewalls of the pair of gate dielectric regions, respectively.

A method, comprising:

• forming multiple memory stacks stacked over one another and stacked over a semiconductor substrate, wherein each memory stack includes a conductive layer, a capacitor dielectric layer over the conductive layer, a lower sacrificial layer over the capacitor dielectric layer, a channel isolation layer, an upper sacrificial layer over the channel isolation layer, and an upper isolation layer over the upper sacrificial layer;
• performing an etch to pattern the memory stacks into multiple columns of memory stack structures wherein trenches separate the multiple columns of memory stack structures from one another;
• performing a first lateral etch to remove outermost portions of the upper sacrificial layer and outermost portions of the lower sacrificial layer in each column of memory stack structures, thereby forming first lower recesses and first upper recesses in sidewalls of the columns of memory stack structures;
• filling the trenches between the columns of memory stack structures, the first lower recesses, and the first upper recesses with conductive material;
• performing a second etch to remove the conductive material from the trenches between the columns of memory stack structures while leaving the conductive material to establish lower conductive regions in the first lower recesses and upper conductive regions in the first upper recesses;
• performing a second lateral etch to remove outermost portions of the channel isolation layer to form second recesses in outer edges of the columns of memory stack structures between the lower conductive regions and upper conductive regions of each memory stack structure;
• and
• forming low-leakage channel material in the trenches and in the second recesses.