Semiconductor device having buried logic conductor type of complementary field effect transistor, method of generating layout diagram and system for same

A semiconductor device comprising a buried logic conductor (BLC) CFET, the BLC CFET including:

• first and second active regions arranged in a stack according to CFET-type configuration with the second active region over the first active region;
• a gate structure proximal to the first and second active regions;
• first and second contact structures correspondingly electrically coupled to the first active region;
• third and fourth contact structures correspondingly electrically coupled to the second active region;
• a first layer of metallization (M_1st layer) over the stack which includes:
• alpha logic conductors configured for logic signals (alpha logic conductors);
• and
• power grid (PG) conductors;
• and
• a layer of metallization below (M_B) the stack (M_B layer) and which includes beta logic conductors;
• a first via structure electrically coupled between a first candidate and a first one of the beta logic conductors in the M_B layer, the first candidate being one of the gate structure or one of the first, second, third or fourth contact structures.

A method of manufacturing a semiconductor device which includes a buried logic conductor (BLC) CFET region, the method comprising forming:

• forming first and second active regions arranged in a first stack with the second active region over the first active region;
• forming a gate structure proximal to the first and second active regions;
• forming first and second contact structures which are arranged in a second stack with the second contact structure over the first contact structure, and which are electrically coupled to the corresponding first and second active regions;
• forming third and fourth contact structures which are arranged in a third stack with the fourth contact structure over the third contact structure, and which are electrically coupled to the corresponding first and second active regions;
• forming alpha logic conductors and power grid (PG) conductors which are in a first layer of metallization, which are correspondingly over the gate structure and the second and fourth contact structures, and which are non-overlapping of each other;
• forming beta logic conductors which are in a buried layer of metallization, which are correspondingly under the gate structure and the first and the third contact structures, and which are non-overlapping of each other, and represent corresponding beta logic conductors in a buried layer of metallization;
• and
• forming a first via structure which is interposed between and electrically couples (A) the gate structure, the first contact structure, the second contact structure, the third contact structure or the fourth contact structure and (B) a first one of the beta logic conductors.