Integrated circuit devices including vertical field-effect transistors

A standard cell comprising:

• a first vertical field effect transistor (VFET) comprising a first bottom source/drain region in a substrate, a first channel region and a first top source/drain region sequentially stacked on the first bottom source/drain region in a vertical direction, wherein the first top source/drain region has a first conductivity type;
• a second VFET comprising a second bottom source/drain region in the substrate, a second channel region and a second top source/drain region sequentially stacked on the second bottom source/drain region in the vertical direction, wherein the second top source/drain region has a second conductivity type that is different from the first conductivity type;
• a common gate layer comprising a first portion that is on a side surface of the first channel region and is a first gate electrode of the first VFET and a second portion that is on a side surface of the second channel region and is a second gate electrode of the second VFET;
• and
• a gate contact that is between the first channel region and the second channel region and contacts the common gate layer,
• wherein each of the first channel region and the second channel region extends longitudinally in a first horizontal direction, and
• the gate contact is spaced apart from the first channel region in a second horizontal direction that is perpendicular to the first horizontal direction.