US 2021/0242200 A1 · NORMALLY OFF III NITRIDE TRANSISTOR

Abstract

A semiconductor device containing an enhancement mode GaN FET on a III-N layer stack includes a low-doped GaN layer, a barrier layer including aluminum over the low-doped GaN layer, a stressor layer including indium over the barrier layer, and a cap layer including aluminum over the stressor layer. A gate recess extends through the cap layer and the stressor layer, but not through the barrier layer. The semiconductor device is formed by forming the barrier layer with a high temperature MOCVD process, forming the stressor layer with a low temperature MOCVD process and forming the cap layer with a low temperature MOCVD process. The gate recess is formed by a two-step etch process including a first etch step to remove the cap layer, and a second etch step to remove the stressor layer.

Claims20

Dependent claims

A semiconductor device, comprising:

a buffer layer;
a first III-N material over the buffer layer;
a second III-N material over the first III-N material;
a third III-N material disposed over the second III-N material, the third III-N having less than 1 atomic percent indium;
an indium aluminum nitride layer over the third III-N, the indium aluminum nitride layer having a stoichiometry of In0.05Al0.95N to In0.30Al0.70N, and a thickness of 1 nanometer to 5 nanometers;
a cap layer of III-N material disposed over the indium aluminum nitride layer;
a gate recess extending through the cap layer and the indium aluminum nitride layer in an enhancement mode gallium nitride field effect transistor (GaN FET), wherein the gate recess does not extend through the third III-N;
a gate dielectric layer disposed over the third III-N in the gate recess;
and
a gate of the enhancement mode GaN FET disposed over the gate dielectric layer in the gate recess.

7 more elements

Dependencies are inferred from the claim text.

Normally off iii nitride transistor

Life of this patent

Normally off iii nitride transistor

Life of this patent

Abstract

Claims20