Vertical transistor device comprising a two-dimensional (2d) material positioned in a channel region of the device and methods of making such vertical transistor devices

A vertical transistor device, comprising:

• a bottom source/drain region;
• a top source/drain region;
• a channel region comprising a plurality of individual layers of 2D material positioned in a vertically stacked arrangement between the bottom source/drain region and the top source/drain region, wherein each of the plurality of layers of 2D material have a periodic crystallographic pattern and wherein, relative to a reference axis of rotation, the periodic crystallographic pattern of one of the plurality of layers of 2D material is rotated relative to the periodic crystallographic pattern of another of the plurality of layers of 2D material;
• and
• a gate structure positioned all around at least a portion of the plurality of individual layers of 2D material.

A vertical transistor device, comprising:

• a bottom source/drain region comprising a doped first semiconductor material;
• a top source/drain region comprising a doped second semiconductor material, wherein the first semiconductor material and the second semiconductor material comprise a same semiconductor material;
• a channel region comprising a plurality of individual layers of 2D material positioned in a vertically stacked arrangement between the bottom source/drain region and the top source/drain region, wherein each of the plurality of layers of 2D material have a periodic crystallographic pattern and wherein, relative to a reference axis of rotation, the periodic crystallographic pattern of one of the plurality of layers of 2D material is rotated relative to the periodic crystallographic pattern of another of the plurality of layers of 2D material, wherein the top source/drain region is positioned on and in contact with an uppermost layer of the plurality of layers of 2D material and the lowermost layer of the plurality of layers of 2D material is positioned on and in contact with the bottom source/drain region;
• and
• a gate structure positioned all around at least a portion of the plurality of individual layers of 2D material.