US 2021/0242091 A1 · VERTICAL FIELD-EFFECT TRANSISTOR DEVICES AND METHODS OF FORMING THE SAME

Abstract

Vertical field-effect transistor (VFET) devices and methods of forming the same are provided. The methods may include forming a lower structure on a substrate. The lower structure may include first and second VFETs, a preliminary isolation structure between the first and second VFETs, and a gate liner on opposing sides of the preliminary isolation structure and between the preliminary isolation structure and the substrate. Each of the first and second VFETs may include a bottom source/drain region, a channel region and a top source/drain region sequentially stacked, and a gate structure on a side surface of the channel region. The preliminary isolation structure may include a sacrificial layer and a gap capping layer sequentially stacked. The methods may also include forming a top capping layer on the lower structure and then forming a cavity between the first and second VFETs by removing the sacrificial layer.

Claims25

Dependent claims

A method of forming an integrated circuit device, the method comprising:

forming a lower structure on a substrate, the lower structure comprising:
a first vertical field-effect transistor (VFET) and a second VFET on the substrate, wherein each of the first VFET and the second VFET comprises a bottom source/drain region in the substrate, a channel region and a top source/drain region that are sequentially stacked on the substrate in a vertical direction, and a gate structure on a side surface of the channel region;
a preliminary isolation structure between the first VFET and the second VFET, wherein the preliminary isolation structure comprises a sacrificial layer and a gap capping layer sequentially stacked on the substrate in the vertical direction;
and
a gate liner on opposing sides of the preliminary isolation structure and between the preliminary isolation structure and the substrate;
forming a top capping layer on the lower structure;
and then
forming a cavity between the first VFET and the second VFET by removing the sacrificial layer.

5 more elements

A method of forming an integrated circuit device, the method comprising:

forming a first preliminary vertical field-effect transistor (VFET) and a second preliminary VFET on a substrate, wherein the first and second preliminary VFETs are spaced apart from each other in a horizontal direction and define a gate opening therebetween, wherein each of the first and second preliminary VFETs comprises a bottom source/drain region in the substrate, a channel region and a mask layer that are sequentially stacked on the substrate in a vertical direction, and a preliminary gate structure on a side surface of the channel region;
sequentially forming a preliminary gate liner and a preliminary sacrificial layer in the gate opening and on the first and second preliminary VFETs;
forming a gate liner and a sacrificial layer in the gate opening by performing a planarization process;
forming a recess in the gate opening on the sacrificial layer by removing a portion of the sacrificial layer;
forming a gap capping layer in the recess;
forming top source/drain openings on the channel regions of the first and second preliminary VFETs, respectively, by removing the mask layer and a portion of the preliminary gate structure of each of the first and second preliminary VFETs;
forming top source/drain regions in the top source/drain openings, respectively;
forming a top capping layer on the top source/drain regions;
and then forming a cavity between the top source/drain regions by removing the sacrificial layer.

6 more elements

A method of forming an integrated circuit device, the method comprising:

forming a preliminary vertical field-effect transistor (VFET) on a substrate, wherein the preliminary VFET comprises a bottom source/drain region in the substrate, a channel region and a mask layer that are sequentially stacked on the substrate in a vertical direction, and a preliminary gate structure on a side surface of the channel region;
sequentially forming a preliminary gate liner, a preliminary sacrificial layer, and a preliminary transistor isolation layer on the preliminary VFET;
performing a planarization process until the mask layer is exposed, thereby forming a gate liner, a sacrificial layer, and a transistor isolation layer, wherein the sacrificial layer comprises a horizontal portion extending parallel to an upper surface of the substrate, and a vertical portion protruding from the horizontal portion and extending on a side surface of the preliminary VFET;
forming a recess on the vertical portion of the sacrificial layer by removing a portion of the vertical portion of the sacrificial layer;
forming a gap capping layer in the recess;
forming a top source/drain opening on the channel region by removing the mask layer and a portion of the preliminary gate structure of the preliminary VFET;
forming a top source/drain region in the top source/drain opening;
forming a top capping layer on the top source/drain region;
forming an opening extending through the top capping layer and the transistor isolation layer and exposing the horizontal portion of the sacrificial layer;
forming a cavity by removing the sacrificial layer through the opening;
and then forming an isolation plug in the opening.

8 more elements

Dependencies are inferred from the claim text.

Vertical field-effect transistor devices and methods of forming the same

Life of this patent

Vertical field-effect transistor devices and methods of forming the same

Life of this patent

Abstract

Claims25