Silicidation of source/drain region of vertical field effect transistor (vfet) structure

A vertical field effect transistor (VFET) structure comprising:

• a substrate;
• fin structures formed on the substrate;
• bottom source/drain regions formed on the substrate between and at opposite sides of lower portions of the fin structures;
• shallow trench isolation (STI) structures formed at sides of the substrate and the bottom source/drain regions;
• and
• top source/drain regions formed on the fin structures, respectively,
• wherein upper portions of the top source/drain regions comprise top silicide layers, respectively.

A method for manufacturing a vertical field effect transistor (VFET) structure, the method comprising:

• providing an intermediate VFET structure comprising a substrate, and fin structures and bottom source/drain regions on the substrate at opposite sides of lower portions of the fin structures;
• siliciding upper portions of the bottom source/drain regions so that bottom silicide layers are formed at upper portions of the bottom source/drain regions;
• and
• forming shallow trench isolation (STI) structures at sides of the substrate and the bottom source/drain regions of which the upper portions are silicided,
• wherein each of the bottom silicide layers has a bar shape.