Flash memory cell and associated high voltage row decoder

A non-volatile memory device comprising:

• an array of flash memory cells organized in rows and columns, each flash memory cell comprising a bit line terminal, a word line terminal, an erase gate terminal, and a source line terminal;
• a high voltage circuit for generating a high voltage;
• and
• a high voltage row decoder comprising an erase gate decoder and a source line decoder, wherein the high voltage row decoder selects one or more rows in response to select signals and wherein the erase gate decoder applies the high voltage to erase gate terminals of the one or more rows or the source line decoder applies the high voltage to source line terminals of the one or more rows;
• wherein the erase gate decoder comprises transistors only of a PMOS type and the source line decoder comprises transistors only of a PMOS type.