Semiconductor Device Performing Implicit Precharge Operation

An apparatus comprising:

• a memory cell array;
• and
• an active control circuit configured to receive an active command and an internal command and generate a state signal,
• wherein the active control circuit is further configured to receive the active command at a first time when the state signal is at a first level and change the state signal to a second level,
• wherein the active control circuit is further configured to receive the active command at a second time subsequent to the first time when the state signal is at the second level and activate a reset signal and change the state signal to the first level,
• wherein the active control circuit is further configured to receive the internal command after a predetermined time period elapses from the first time and keep the state signal at the second level, and
• wherein the active control circuit is further configured to receive the internal command after the predetermined time period elapse from the second time and change the state signal to the second level.