Metastable resistant latch

A method to prevent metastability in an input/output (IO) circuitry of a memory device comprising a latch, comprising:

• receiving a latched output signal;
• determining whether the latched output signal is a logic 0 or a logic 1;
• in response to determining that the latched output signal is not a logic 0 or a logic 1, determining whether a memory operation associated with the latch is to avoid capacitive loading on an internal feedback path of the latch;
• and
• in response to determining that the memory operation is to avoid the capacitive loading, using a cascaded timing arbiter latch with at least one timing arbiter and at least one inverter to minimize the capacitive loading.

A memory device, comprising:

• a latch configured to receive a data signal and a data strobe clock signal to latch an output data signal, wherein the latch comprises:
• a plurality of NAND-type timing arbiters comprising a plurality of cross-coupled NAND gates;
• and
• plurality of inverters, wherein the plurality of NAND-type timing arbiters and the plurality of inverters alternate and are disposed in a cascaded architecture, wherein the plurality of NAND-type timing arbiters and the plurality of inverters are configured to receive the data signal and the data strobe clock signal to provide the output data signal.