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US 2021/0241811 A1Published application
Power mode wake-up for memory on different power domains
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChe-Ju Yeh, Hau-Tai Shieh, Yi-Tzu Chen
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Abstract
A memory device includes an array of memory cells and a plurality of peripheral circuits operably coupled to the memory array. A power control circuit may be configured to individually control an application of power to each of the plurality of peripheral circuits and the array of memory cells. Inserting a switch device across the different power domains to achieve the same sequential wake-up path for the peripheral circuits connected to different power domains reduces peak current.
Claims20
A power control system, comprising:
- a power supply rail configured to receive a power supply voltage signal;
- a first header circuit connected to the power supply rail and having a first output terminal configured to provide a first output voltage signal in a first power domain;
- a second header circuit connected to the power supply rail and having a second output terminal configured to provide a second output voltage signal in a second power domain;
- and
- a control switch connected between the first and second header circuits configured to selectively interconnect the first and second output terminals.
2 more elements
A memory system, comprising:
- an array of memory cells;
- a first plurality of peripheral circuits connected to the array of memory cells;
- a second plurality of peripheral circuits connected to the array of memory cells;
- a power supply rail configured to receive a power supply voltage signal;
- a first power control cell including:
- a first header circuit connected to the power supply rail and having a first output terminal connected to the first plurality of peripheral circuits to provide a first output voltage signal in a first power domain;
- and
- a second header circuit connected to the power supply rail and having a second output terminal connected to the second plurality of peripheral circuits to provide a second output voltage signal in a second power domain;
- a second power control cell including:
- a third header circuit connected to the power supply rail and having a third output terminal connected to a third plurality of peripheral circuits to provide a third output voltage signal in a third power domain;
- and
- the second header circuit connected to the power supply rail and having the second output terminal connected to the second plurality of peripheral circuits to provide the second output voltage signal in a second power domain;
- a first control switch connected between the first and second header circuits configured to selectively interconnect the first and second output terminals, and a second control switch connected between the second and third header circuits configured to selectively interconnect the second and third output terminals.
10 more elements
A method, comprising:
- providing a memory array;
- providing a first plurality of peripheral circuits connected to the memory array;
- providing a second plurality of peripheral circuits connected to the memory array;
- providing a first header circuit having a first output terminal, wherein the first header circuit is connected to a power supply rail and the first output terminal is connected to the first plurality of peripheral circuits;
- providing a second header circuit having a second output terminal, wherein the second header circuit is connected to the power supply rail and the second output terminal is connected to the second plurality of peripheral circuits;
- turning off the first header circuit to disconnect the first plurality of peripheral circuits from the power rail in response to a sleep mode command;
- turning off the second header circuit to disconnect the second plurality of peripheral circuits from the power rail in response to the sleep mode command;
- turning on the first header circuit to connect the first plurality of peripheral circuits to a first supply voltage in a first power domain in response to a wake-up mode command;
- and
- interconnecting the output terminals of the first and second header circuits in response to the wake-up command to supply the first supply voltage to the second plurality of peripheral circuits without turning on the second header circuit.
7 more elements
Dependencies are inferred from the claim text.