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US 2021/0241805 A1Published application
Write leveling
AssigneeMicron Technology, Inc.
InventorsDaniel B. Penney, Gary L. Howe
Life of this patent
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Abstract
A memory device includes a command interface configured to receive a write command and internal write adjust (IWA) circuitry. The IWA circuitry is configured to receive the write command from the command interface, generate an internal write signal (IWS) based upon the received write command and train a data strobe (DQS) signal to generate a DQS signal having a set amount of phase alignment with a clock (CLK) of the memory device to capture a data signal (DQ) using the IWS.
Claims20
A memory device, comprising:
- a command interface configured to receive a write command;
- and
- internal write adjust (IWA) circuitry configured to:
- receive the write command from the command interface;
- generate an internal write signal (IWS) based upon the write command;
- and
- train a data strobe (DQS) signal to generate a DQS signal having a set amount of phase alignment with a clock (CLK) of the memory device to capture a data signal (DQ) using the IWS.
4 more elements
A method, comprising:
- implementing internal write leveling in a memory device, comprising:
- setting a value in a mode register of the memory device, wherein the value corresponds to a number of clock cycles of a clock (CLK) by which transmission of an internal write signal (IWS) is adjusted;
- determining whether the value in the mode register causes phase alignment between an internal data strobe (DQS) signal and the CLK to be outside of a predetermined amount of phase mismatch;
- and
- adjusting the value in the mode register to alter the phase alignment between the DQS signal and the CLK to be within the predetermined amount of phase mismatch.
2 more elements
An internal write adjust apparatus, comprising:
- a mode register configured to transmit a control signal based upon a stored indication in the mode register;
- and
- a multiplexer configured to receive the control signal and a write command, wherein the multiplexer is configured to selectively transmit the write command based on a value of the control signal, wherein the mode register is configured to receive the stored indication as indicative of whether a phase alignment between an internal data strobe (DQS) signal of a memory device and a clock of the memory device are outside a predetermined amount of phase mismatch with one another.
Dependencies are inferred from the claim text.