US 2021/0241803 A1 · MEMORY DEVICE AND POWER MANAGEMENT METHOD USING THE SAME

Abstract

A memory device that is operable at a first voltage domain and a second voltage domain includes a memory array, a power saving mode pin and a word line level shifter circuit. The memory array operates at the first voltage domain. The power saving mode pin is configured to receive a power saving mode enable signal that is at the second voltage domain. The power saving mode enable signal is configured to enable a power saving mode of the memory device. The word line level shifter circuit is coupled to the memory array and the power saving mode pin, and is configured to clamp a word line of the memory array to a predetermined voltage level that corresponds to a first logic state during the power saving mode of the memory device.

Claims20

Dependent claims

A memory device operable at a first voltage domain and a second voltage domain, the memory device comprising:

a memory array, configured to operate at the first voltage domain;
a power saving mode pin, configured to receive a power saving mode enable signal that is at the second voltage domain, wherein the power saving mode enable signal is configured to enable a power saving mode of the memory device;
and
a word line level shifter circuit, coupled to the memory array and the power saving mode pin, configured to clamp a word line of the memory array to a predetermined voltage level that corresponds to a first logic state during the power saving mode of the memory device.

1 more element

A memory device operable at a first voltage domain and a second voltage domain, the memory device comprising:

a memory array, configured to operate at the first voltage domain;
a first logic circuit, configured to operate at the first voltage domain when the memory device is in a first power saving mode and to operate at the second voltage domain when the memory device is not in the first power saving mode;
and
a word line level shifter circuit, coupled to the memory array, configured to clamp a word line of the memory array to a predetermined voltage level that corresponds to a first logic state during the first power saving mode of the memory device.

1 more element

A power management method, adapted to a memory device operable at a first voltage domain and a second voltage domain, the method comprising:

determining whether the memory device operates in a power saving mode according to a power saving mode enable signal;
and
in response to determining that the memory device operates in the power saving mode, clamping a word line of a memory array to a predetermined voltage level that corresponds to a first logic state during the power saving mode.

Dependencies are inferred from the claim text.

Facts

Application

17/031,925Filed 25 Sep 2020

Priority

31 Jan 2020

Published

5 Aug 2021

Term ends

Not estimatedThe source records don’t support an estimate.

Classification6 codes

G11C 5/148
Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels: details…
G11C 5/147
Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels: voltage…
G11C 8/08
Arrangements for selecting an address in a digital store: word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down…
G11C 11/417
Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction: for memory cells of the field-effect type

Memory device and power management method using the same

Life of this patent

Memory device and power management method using the same

Life of this patent

Abstract

Claims20