Performance and area efficient synapse memory cell structure

A device comprising:

• a synapse memory system, comprising:
• a plurality of synapse memory cells disposed at cross points of a plurality of axon lines and a plurality of dendrite lines, each synapse memory cell including a plurality of analog memory devices, each synapse memory cell being configured to store a weight value according to an output level of a write signal, the weight value to be stored in each synapse memory cell being one value of at least three different values, the plurality of analog memory devices being combined to constitute each synapse memory cell;
• a write portion configured to write the weight value to each synapse memory cell, the write portion comprising a write driver and an output controller, the write driver being configured to output the write signal to a subject synapse memory cell, the subject synapse memory cell being one of the plurality of synapse memory cells, the subject synapse memory cell being selected to store the weight value, the output controller being configured to control the output level of the write signal of the write driver;
• and
• read drivers configured to read the weight value stored in the synapse memory cells.

A synapse memory system, comprising:

• an analog memory, comprising:
• a free layer, the free layer including fixed regions disposed at end portions thereof and a data region interposed between the fixed regions;
• and
• a plurality of pinning layers disposed on each respective fixed region,
• wherein excitation of the fixed regions by the pinning layers induces opposed magnetic fields in each respective fixed region, the opposed magnetic fields defining a domain wall at an inflection point of the opposed magnetic fields of the fixed regions.

An analog memory for use in a synapse memory cell, comprising:

• a free layer, the free layer including fixed regions disposed at end portions thereof and a data region interposed between the fixed regions;
• and
• a plurality of pinning layers disposed on each respective fixed region,
• wherein excitation of the fixed regions by the pinning layers induces opposed magnetic fields in each respective fixed region, the opposed magnetic fields defining a domain wall at an inflection point of the opposed magnetic fields of the fixed regions.

A synapse memory system, comprising:

• a synapse memory, comprising:
• a plurality of synapse memory cells disposed at cross points of a plurality of axon lines and a plurality of dendrite lines, wherein a length of the synapse memory along an axon line portion compared to a length of the synapse memory along a dendrite line portion defines an aspect ratio;
• a first plurality of peripheral devices operably coupled to the axon line portion of the synapse memory;
• and
• a second plurality of peripheral devices operably coupled to the dendrite line portion of the synapse memory,
• wherein the aspect ratio of the synapse memory approximates 1:1.