US 2021/0240906 A1 · Integrated Circuit Layout Validation Using Machine Learning

Abstract

Systems, methods, and devices are described herein for integrated circuit (IC) layout validation. A plurality of IC patterns are collected which include a first set of patterns capable of being manufactured and a second set of patterns incapable of being manufactured. A machine learning model is trained using the plurality of IC patterns. The machine learning model generates a prediction model for validating IC layouts. The prediction model receives data including a set of test patterns comprising scanning electron microscope (SEM) images of IC patterns. Design violations associated with an IC layout are determined based on the SEM images and the plurality of IC patterns. A summary of the design violations is provided for further characterization of the IC layout.

Claims20

Dependent claims

A computer-implemented method comprising:

generating, by a machine learning model, a prediction model for validating IC layouts;
receiving, by the prediction model, data comprising a set of test patterns comprising scanning electron microscope (SEM) images of IC patterns;
determining, by the prediction model, design violations associated with an IC layout based on the SEM images and the plurality of IC patterns by:
generating a compilation of pixel patterns including a first set of pixel patterns capable of being manufactured and a second set of pixel patterns incapable of being manufactured;
and
identifying differences between the IC layout with the first set of pixel patterns and the second set of pixel patterns, wherein the design violations comprise the differences;
and
providing a summary of the design violations for further characterization of the IC layout.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application

17/233,699Filed 19 Apr 2021

Priority

16 Sep 2019

Published

5 Aug 2021

Term ends

Not estimatedThe source records don’t support an estimate.

Classification15 codes

G06F 30/398
Circuit design at the physical level: design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or…
G06T 7/001
Industrial image inspection: using an image reference approach
G06F 30/27
Design optimisation, verification or simulation: using machine learning, e.g. artificial intelligence, neural networks, support vector machines…
G06N 3/0464
Architecture, e.g. interconnection topology: convolutional networks [CNN, ConvNet]

Integrated Circuit Layout Validation Using Machine Learning

Life of this patent

Integrated Circuit Layout Validation Using Machine Learning

Life of this patent

Abstract

Claims20