Cell row arrangement in regions of integrated circuit layout
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChun-Yao KU, Wen-Hao CHEN, Ming-Tao YU
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AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChun-Yao KU, Wen-Hao CHEN, Ming-Tao YU
Estimating the term…
A method of generating a layout design of an integrated circuit. The method includes forming a first region having at least two first-type cell rows extending in a first direction. Each one of the first-type cell rows has a first row height measured along a second direction perpendicular to the first direction. The method also includes forming a second region having at least two second-type cell rows extending in the first direction. Each one of the second-type cell rows has a second row height measured along the second direction. The first region is adjacent to the second region, and the first row height of the first-type cell rows is different from the second row height of the second-type cell rows.
A method of generating, by a processor, a layout design of an integrated circuit, the method comprising:
A computer program code stored on a non-transitory computer-readable medium for generating a layout design, the computer program code is configured to cause a system having at least one processor to execute:
A method of generating, by a processor, a layout design of an integrated circuit, the method comprising:
Dependencies are inferred from the claim text.