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US 2021/0240656 A1Published application
SPI Broadcast Mode
AssigneeInfineon Technologies AG
InventorsChristoph Rumpler, Reinhard-Wolfgang Jungmaier, Dennis Noppeney, Saverio Trotta
Life of this patent
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Abstract
In an embodiment, a method for writing to a set of serial peripheral interface (SPI) slaves coupled to an SPI bus includes: disabling master in slave out (MISO) drivers of the set of SPI slaves using the SPI bus; after disabling the MISO drivers, setting respective slave selection terminals of the set of SPI slaves to an active state; and after setting the respective slave selection terminals of the set of SPI slaves to the active state, simultaneously writing data to the set of SPI slaves using a master out slave in (MOSI) line.
Claims23
A method for writing to a set of serial peripheral interface (SPI) slaves coupled to an SPI bus, the method comprising:
- disabling master in slave out (MISO) drivers of the set of SPI slaves using the SPI bus;
- after disabling the MISO drivers, setting respective slave selection terminals of the set of SPI slaves to an active state while keeping the MISO drivers of the set of SPI slaves disabled;
- and
- after setting the respective slave selection terminals of the set of SPI slaves to the active state, simultaneously writing data to the set of SPI slaves using a master out slave in (MOSI) line.
1 more element
A system comprising:
- a serial peripheral interface (SPI) bus comprising a master out slave in (MOSI) line, and a master in slave out (MISO) line;
- an SPI master comprising a MOSI terminal coupled to the MOSI line, a MISO terminal coupled to the MISO line, a first slave selection terminal, and a second slave selection terminal;
- a first SPI slave comprising a MOSI terminal coupled to the MOSI line, a MISO terminal coupled to the MISO line, a first MISO driver having an output coupled to the MISO terminal of the first SPI slave, and a first slave selection terminal coupled to the first slave selection terminal of the SPI master;
- and
- a second SPI slave comprising a MOSI terminal coupled to the MOSI line, a MISO terminal coupled to the MISO line, a second MISO driver having an output coupled to the MISO terminal of the second SPI slave, and a second slave selection terminal coupled to the second slave selection terminal of the SPI master, wherein the SPI master is configured to:
- disable the first and second MISO drivers using the SPI bus;
- after disabling the first and second MISO drivers, set the first and second slave selection terminals of the SPI master to an active state while keeping the first and second MISO drivers disabled;
- and
- after setting the first and second slave selection terminals of the SPI master to an active state, simultaneously write data to the first and second SPI slaves using the MOSI line.
6 more elements
A system comprising:
- a serial peripheral interface (SPI) bus comprising a master out slave in (MOSI) line, and a master in slave out (MISO) line;
- an application processor having an SPI master comprising a MOSI terminal coupled to the MOSI line, a MISO terminal coupled to the MISO line, a first slave selection terminal, and a second slave selection terminal;
- a first device having a first register bank and a first SPI slave comprising a MOSI terminal coupled to the MOSI line, a MISO terminal coupled to the MISO line, a first MISO driver having an output coupled to the MISO terminal of the first SPI slave, and a first slave selection terminal coupled to the first slave selection terminal of the SPI master;
- and
- a second device having a second register bank and a second SPI slave comprising a MOSI terminal coupled to the MOSI line, a MISO terminal coupled to the MISO line, a second MISO driver having an output coupled to the MISO terminal of the second SPI slave, and a second slave selection terminal coupled to the second slave selection terminal of the SPI master, wherein the application processor is configured to:
- disable the first and second MISO drivers using the SPI master,
- after disabling the first and second MISO drivers, set the first and second slave selection terminals of the SPI master to an active state while keeping the first and second MISO drivers disabled, and
- after setting the first and second slave selection terminals of the SPI master to an active state, simultaneously write data to the first and second register banks via the SPI bus using the SPI master.
5 more elements
Dependencies are inferred from the claim text.