Memory module with local synchronization and method of operation

A memory module operable in a computer system having a memory controller and a system bus including one or more clock signal lines, a set of control signal lines and a plurality of sets of n-bit wide data/strobe signal lines, where n is an integer larger than one, comprising:

• a control circuit configurable to receive a system clock from the memory controller via the one or more clock signal lines, and input address and control (C/A) signals from the memory controller via the set of control signal lines, and to output a module clock signal, module C/A signals and data buffer control signals in response to the system clock and the input C/A signals;
• memory devices organized in one or more ranks;
• and
• a plurality of data buffers configurable to receive the module clock signal and the data buffer control signals from the control circuit;
• wherein:
• a respective data buffer of the plurality of data buffers is coupled to a respective group of the memory devices and includes a respective n-bit-wide data path and logic configurable to control the respective n-bit-wide data path in response to the data buffer control signals, the respective group of the memory devices including at least one memory device in each of the one or more ranks, the respective n-bit-wide data path including at least one programmable delay element controlled by the logic;
• the respective data buffer is configurable to generate, in response to receiving the module clock signal, a respective local clock signal that is phase-locked with the module clock signal and has a respective programmable delay from the module clock signal;
• and
• the respective group of the memory devices is configurable to receive the module C/A signals from the control circuit and the respective local clock signal, and to communicate respective data and data strobe signals with the memory controller in response to the module C/A signals and the respective local clock signal, the respective data and data strobe signals being communicated via the respective n-bit wide data path and a respective set of the plurality of sets of n-bit wide data/strobe signal lines.