Method and apparatus for eliminating bit disturbance errors in non-volatile memory devices

A system comprising:

• a data storage module;
• and
• a processing circuitry operatively coupled to the data storage module, wherein the processing circuitry is configured to perform the operations of:
• performing a first read from an address in the data storage module by using a first read voltage;
• storing, in a first register, data that is retrieved from the data storage module as a result of the first read;
• performing a second read from the address by using a second different read voltage;
• storing, in a second register, data that is retrieved from the data storage module as a result of the second read;
• detecting whether a weak bit condition is present at the address based on the data that is stored in the first register and the data that is stored in the second register, and
• correcting the weak bit condition when the weak bit condition is present at the address.

A sensor comprising:

• a sensor controller;
• one or more sensing elements operatively coupled to the sensor controller;
• and
• a memory operatively coupled to the controller, the memory including a data storage module and a processing circuitry operatively coupled to the data storage module, the processing circuitry being configured to perform the operations of:
• performing a first read from an address in the data storage module by using a first read voltage;
• storing, in a first register, data that is retrieved from the data storage module as a result of the first read;
• performing a second read from the address by using a second different read voltage;
• storing, in a second register, data that is retrieved from the data storage module as a result of the second read;
• detecting whether a weak bit condition is present at the address based on the data that is stored in the first register and the data that is stored in the second register;
• and
• correcting the weak bit condition when the weak bit condition is present at the address.

A non-transitory computer-readable medium storing one or more processor executable instructions, which when executed by at least one processor cause the processor to perform the operations of:

• performing a first read from an address in a data storage module by using a first read voltage;
• storing, in a first register, data that is retrieved as a result of the first read;
• performing a second read from the address by using a second read voltage;
• storing, in a second register, data that is retrieved as a result of the second read;
• detecting whether the data that is stored in the first register matches the data that is stored in the second register;
• and
• overwriting the address with the data stored in the second register, the address being overwritten in response to the data stored in the first register not matching the data stored in the second register.